A phase-locked loop or phase lock loop (PLL) is an electrical circuit that generates an output signal. A phase of the output signal may be related to a phase of an input reference signal. A PLL circuit may comprise a phase frequency detector (PFD), a charge pump (CP), a loop filter, and a voltage-controlled oscillator (VCO). In use, the PFD may compare the phase of the input reference signal with the phase of a signal derived from an output of the VCO. The PLL may adjust the frequency of its oscillator output to keep the two phases matched. To form a PLL circuit, the PFD may generate an output representing an error between the input reference and the oscillator. The error signal may be fed to the loop filter, which may integrate the signal to smooth it. Then, the smoothed signal may be fed into the VCO, which may generate an output signal with a frequency that is proportional to the smoothed signal (e.g., a tuning voltage signal). The VCO output may also be fed back to the PFD to complete the loop structure of the PLL.
Frequency is a time derivative of phase. Keeping the input and output phase in a locked state may imply keeping the input and output frequencies in a locked state. Consequently, a phase-locked loop may track an input frequency, or it may generate a frequency that is a multiple of the input frequency.
Conventionally, a PLL may comprise a passive loop filter (PLF) that operates in a passive mode. No active internal components substituting external loop filter may be included in the PLF. Consequently, the PLF may need one or more external capacitors to achieve a required loop dynamic. The external capacitors may occupy precious space on the PLL die, which may be undesirable especially when the external capacitors have relatively large capacitances (e.g., greater than 1 nanofarad (nF)).